Published | 2022-02-28 |
Platform | Udemy |
Rating | 5.00 |
Number of Reviews | 1 |
Number of Students | 1 |
Price | $49.99 |
Instructors |
Vikas Sachdeva
|
Subjects |
Learn everything about VLSI and semiconductor design flow
The course covers the following topics
· Introduction to VLSI
· Semiconductor market overview
· Design Complexity
· Semiconductor future trends and enablers
· AI Accelerators
· IOT
· Automotive
· Overview of VLSI Design Flow
· Soft IPs
· Soft IPs Flow
· Hard IPs
· Hard IP Flow
· Analog IPs
· Analog IPs Flow
· System on a chip (SOC)
· SOC Flow
· Software vs Hardware in SoC
· FPGA vs ASIC
· FPGA Architecture
· FPGA Flow
· Specification
· Tools used in Specification
· Architecture
· Tools used in architecture
· RTL design and behavioural coding
· RTL Linting
· Verification
· Simulation and Dynamic Verification
· Emulation
· Static Verification
· Formal Verification
· Assertion Based Verification
· CDC Verification
· Logic Synthesis
· Synthesis Flow
· Synthesis inputs and outputs
· Synthesis tools
· Equivalence Checking
· Tools for equivalence checking
· Testing
· Defect
· Defect Modeling
· Scan Chains
· Scan Flipflop
· Test mode operation
· Shift and Capture operation
· Scan Insertion Design Flow
· Board level testing and diagnosis
· JTAG
· Built-in self-test (BIST)
· Analog circuit testing
· Tools for DFT and testing
· Power consumption
· Dynamic power
· Clock Gating
· Multi-voltage design
· Power tools
· Post synthesis STA
· STA Definition
· STA Features
· Types of timing paths
· Setup check
· Hold Check
· STA - Inputs and Outputs
· Timing Report
· STA Tools
· Please and Route
· Physical Design Flow
· Partitioning
· Floorplanning
· Clock tree synthesis
· Routing
· Timing analysis and closure
· Physical Verification
· PnR - Tools
· Signoff STA
· Signoff checks
· Gate level verification
· ECO Flow
· Fabrication
· IC Packaging
· IC Testing
· Roles in architecture
· Roles in frontend
· Roles in the backend
· Roles in EDA companies